Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistor-based circuits into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device. The term is no longer as common as it once was, as chips have increased in complexity into the hundreds of millions of transistors.thw size of the chip is 60nm. Now they are founding 45 nm in size.
DESIGNING OF VLSI:
The design flow of the VLSI design is follows:
- Specification
- Methodology
- Rtl coding
- Rtl verification
- Synthesis
- documentation
SPECIFICATION:
Before go to the vlsi designing, need to the decide, which project or device are going to design,, that is called specification.
For example, if the project about RS flip-flop, that is the specification of the designing.
METHODOLOGY:
For each and every project or chip coding, first the designer has to decide , which methodology can use and while decide it should be very flexible when create or write coding . There are two types of methodology are available,
- Top down approach
- Bottom up approach
In the VLSI coding most of the designer prefer top down approach. Because it is very easy to analysis when it compares to the bottom up approach.
In top down approach , coding are written from main module . after that, it starts a sub module hence it is very easy to understand.
In bottom up approach , we analyze from the sub module and then it goes to main concept of the program. It is tuff to understand.
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THE VLSI DESIGN PROCESS:
RTL CODING:
RTL coding means write a coding for the resistor, transistor and logic gates. It means write the coding for data flow of the circuit , behavior of the circuit and connection of the logic gates.
For write the RTL coding, designer’s use HDL languages. HDL means Hardware Description Language. Here we are going to describe the coding for how the hardware or circuit has to work. That is called HDL.
HDL has two types of language. They are,
- Verilog HDL
- VHDL (Very high speed integrated circuit HDL)
Verilog HDL:
Verilog stands for verify logic. Verilog is a hardware description language (HDL) used to model electronic systems. The language (sometimes called Verilog HDL) supports the design, verification, and implementation of analog, digital, and mixed-signal circuits at various levels of abstraction.
The designers of Verilog wanted a language with syntax similar to the C programming language so that it would be familiar to engineers and readily accepted. The language is case-sensitive, has a preprocessor like C, and the major control flow keywords, such as "if" and "while", are similar. The formatting mechanism in the printing routines and language operators and their precedence are also similar.
The language differs in some fundamental ways. Verilog uses Begin/End instead of curly braces to define a block of code. The definition of constants in Verilog require a bit width along with their base, consequently these differ. Verilog 95 and 2001 don't have structures, pointers, or recursive subroutines, however SystemVerilog now includes these capabilities. Finally, the concept of time —so important to a HDL— won't be found in C.
The language differs from a conventional programming language in that the execution of statements is not strictly sequential. A Verilog design consists of a hierarchy of modules. Modules are defined with a set of input, output, and bidirectional ports. Internally, a module contains a list of wires and registers. Concurrent and sequential statements define the behaviour of the module by defining the relationships between the ports, wires, and registers. Sequential statements are placed inside a begin/end block and executed in sequential order within the block. But all concurrent statements and all begin/end blocks in the design are executed in parallel, qualifying Verilog as a Dataflow language.
A subset of statements in the language is synthesizable. If the modules in a design contain only synthesizable statements, software can be used to transform or synthesize the design into a netlist that describes the basic components and connections to be implemented in hardware. The netlist may then be transformed into, for example, a form describing the standard cells of an integrated circuit (e.g. an ASIC) or a bitstream for a programmable logic device (e.g. a FPGA).
Verilog-95
With the increasing success of VHDL at the time, Cadence decided to make the language available for open standardization. Cadence transferred Verilog into the public domain under the Open Verilog International (OVI) (now known as Accellera) organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95.
In the same time frame Cadence initiated the creation of Verilog-A to put standards support behind its analog simulator Spectre. Verilog-A was never intended to be a standalone language and is a subset of Verilog-AMS which encompassed Verilog-95.
Verilog 2001
Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that users had found in the original Verilog standard. These extensions became IEEE Standard 1364-2001 known as Verilog-2001.
Verilog-2001 is a significant upgrade from Verilog-95. First, it adds explicit support for (2's complement) signed nets and variables. Previously, code authors had to perform signed-operations using awkward bit-level manipulations (for example, the carry-out bit of a simple 8-bit addition required an explicit description of the boolean-algebra to determine its correct value.) The same function under Verilog-2001 can be more succinctly described by one of the built-in operators: +, -, /, *, >>>. A generate/endgenerate construct (similar to VHDL's generate/endgenerate) allows Verilog-2001 to control instance and statement instantiation through normal decision-operators (case/if/else).
Not to be confused with SystemVerilog, Verilog 2005 (IEEE Standard 1364-2005) consists of minor corrections, spec clarifications, and a few new language features (such as the uwire keyword.)
A separate part of the Verilog standard , Verilog-AMS, attempts to integrate analog and mixed signal modelling with traditional Verilog.
Systemverilog is a superset of Verilog-2005, with many new features and capabilities to aid design-verification and design-modeling.
The advent of High Level Verification languages such as OpenVera, and Verisity's E language encouraged the development of Superlog by Co-Design Automation Inc. Co-Design Automation Inc was later purchased by Synopsys. The foundations of Superlog and Vera were donated to Accellera, which later became the IEEE standard P1800-2005: SystemVerilog.
//** 4-Bit Adder *****************************
module FourBitAdder(sum, c_out, x, y, c_in);
output [3:0] sum;
output c_out;
input [3:0] x, y;
input c_in;
wire c1, c2, c3;
full adder fa0(sum[0], c1, x[0], y[0], c_in);
full adder fa1(sum[1], c2, x[1], y[1], c1);
fulladder fa2(sum[2], c3, x[2], y[2], c2);
fulladder fa3(sum[3], c_out, x[3], y[3], c3);
endmodule
//*******************************************
// VeriLogger Pro: Basic Verilog Simulation
// (Tutorial 7 in SynaptiCAD Series)
//*******************************************
VHDL:
VHDL is an acronym for Very high speed integrated circuit (VHSIC) Hardware Description Language which is a programming language that describes a logic circuit by function, data flow behavior, and/or structure. This hardware description is used to configure a programmable logic device (PLD), such as a field programmable gate array (FPGA), with a custom logic design. The general format of a VHDL program is built around the concept of BLOCKS which are the basic building units of a VHDL design. Within these design blocks a logic circuit of function can be easily described.
A VHDL design begins with an ENTITY block that describes the interface for the design. The interface defines the input and output l1ogic signals of the circuit being designed. The ARCHITECTURE block describes the internal operation of the design. Within these blocks are numerous other functional blocks used to build the design elements of the logic circuit being created.
After the design is created, it can be simulated and synthesized to check its logical operation. SIMULATION is a bare bones type of test to see if the basic logic works according to design and concept. SYNTHESIS allows timing factors and other influences of actual field programmable gate array (FPGA) devices to effect the simulation thereby doing a more thorough type of check before the design is committed to the FPGA or similar device.
Many software packages used for VHDL design also support schematic capture which takes a logic schematic or state diagram and translates it into VHDL code. This, in turn, makes the design process a lot easier. However, to fine tune any design, it helps to be familiar with the actual VHDL code.
EXAMPLE:
library ieee;
use ieee.std_logic_1164.all;
entity adder4 is
port (
signal a,b: in std_logic_vector (3 downto 0);
signal cin: in std_logic;
signal sum: out std_logic_vector(3 downto 0);
signal cout: out std_logic
);
end adder4;
architecture behavior of adder4 is
signal c: std_logic_vector(4 downto 0);
begin
process (a,b,cin,c)
begin
c(0) <= cin;
for i in a'range loop
sum(i) <= a(i) xor b(i) xor c(i);
c(i+1) <= (a(i) and b(i)) or
(c(i) and (a(i) or b(i)));
end loop;
cout <= c(c'HIGH);
end process;
end behavior;
RTL VERIFICATION:
In this section we will test the output and the waveforms before we make the circuit
By write the testbench, we can check the different output by giving different inputs.
So this verification may reduce the errors.
In this tutorial, you will create, build, and simulate a project.
VeriLogger uses a project to control all aspects of simulation and design including specifying the files to be simulated, controlling simulation options, and setting watches on signals.
The project also stores the hierarchical structure of the Verilog components contained in the design and displays this information on the tree control in the Project window.
EXAMPLE:
//add4test.v File ***************************
Module testbed();
reg c_in;
reg [3:0] y;
reg [3:0] x;
wire c_out;
wire [3:0]sum;
FourBitAdder A1 (sum, c_out, x, y, c_in);
Initial
Begin
x = 4'b0001; y = 4'b0001; c_in = 1'b0;
#25 x = 4'b0001; y = 4'b0010;
#25 x = 4'b0010; y = 4'b0011;
#25 x = 4'b0001; y = 4'b1111;
#25 x = 4'b0001; y = 4'b1111; c_in = 1'b1;
#25 x = 4'b1000; y = 4'b1111; c_in = 1'b0;
#25 x = 4'b0001; y = 4'b0001; c_in = 1'b1;
#25 x = 4'b0001; y = 4'b0010;
#25 x = 4'b0010; y = 4'b0011;
#25 x = 4'b0011; y = 4'b1111;
end
Initial
#250 $finish;
End module
PROCEDURE OF VERIFICATION:
1. Add Files to the Project
2. Build the Tree and use the Editor Windows
3. Simulate the Project
4. Watch and View Internal Signals
5. Save the Project, Waveforms and Source Code.
FUSING:
After write the coding, designers will fuse the coding into the VLSI chip. As same as embedded system.
CIRCUIT VERIFICATION:
After fuse the coding into the chip, designers will go to the circuit of the project. Whatever they need for circuit they will do it. After make the circuit they will set the VLSI chip into the circuit.
Designers will verify the circuit connections and make sure every components works correctly.
ADVANTAGES OF VLSI:
- Smaller size
- Lower cost
- Lower power
- Higher reliability
- More functionality
DIS ADVANTAGES OF VLSI:
- Long design and fabrication time
- Higher risk to project
| VLSI Designs: Front-end | |
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| Design Entry: | |
| • | VHDL/Verilog/ Mixed |
| • | SystemC |
| • | SystemVerilog |
| | |
| Simulation: | |
| • | Functional |
| • | Timing |
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| Coverage: | |
| • | Line, Condition, FSM, Toggle |
| Synthesis: | |
| • | Target |
| Equivalence Checking | |
| Equivalence Checking Static Timing Analy | |
